1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a capacitor and a method of manufacturing the same.
2. Description of the Prior Art
As shown in FIG. 1, the capacitors constituting the planar FeRAM (Ferroelectric Random Access Memory) have a stripe-like lower electrode 101 called a plate line, a ferroelectric film 102 formed on the lower electrode 101, and a plurality of upper electrodes 103 formed on the ferroelectric film 102. Then, the capacitors are formed on the stripe-like lower electrode 101 as many as the upper electrodes 103.
Then, steps of forming the capacitor in the prior art, viewed from a I—I cross section in FIG. 1, will be explained hereunder.
First, as shown in FIG. 2A, a first conductive film 101a, a ferroelectric film 102, and a second conductive film 103a are formed sequentially on an insulating film 100. Then, a first resist pattern (not shown) having an upper electrode shape is formed on the second conductive film 103a, and then the second conductive film 103a is etched while using the first resist pattern as a mask. Then, as shown in FIG. 2B, the second conductive film 103a left after the first resist pattern is removed is employed as the upper electrode 103.
Then, as shown in FIG. 2C, a stripe-like second resist pattern 104 is formed on the ferroelectric film 102 to have a shape that coincides with both side edges of the upper electrode 103. Then, as shown in FIG. 2D, the ferroelectric film 102 is etched by using the second resist pattern 104 as a mask.
The second resist pattern 104 is removed, and then a stripe-like third resist pattern 105 is formed on the first conductive film 101a to have a shape that coincides with both side edges of the upper electrode 103 and the ferroelectric film 102. Then, as shown in FIG. 2E, the first conductive film 101a is etched by using the third resist pattern 105 as a mask, whereby the first conductive film 101a being left is employed as the lower electrode 101. After this, a planar shape shown in FIG. 1 can be obtained substantially by removing the third resist pattern 105.
As the material of the ferroelectric film 102 constituting such capacitor, PZT, PLZT, SBT, etc. are used. Also, as the material of the conductive films 101a, 103a, Pt, Ir, Ru, etc. are used. Since all materials have poor reactivity, the plasma etching having the strong sputter characteristic is employed mainly to pattern these films. In such etching process, as shown in FIGS. 2D and 2E, a product 106 is ready to adhere to the side wall of the pattern during the etching. The product 106 is conductive because it contains metal material. Thus, if the product 106 remains as it is, such product 106 causes the leakage current to flow between the upper and lower electrodes 103, 101 of the capacitor.
In other words, if the shape of the second resist pattern 104 or the third resist pattern 105 that is employed to pattern the ferroelectric film 102 or the lower electrode 101 is shaped to coincide with both side edges of the upper electrode 103, the conductive etching product 106 is adhered to the side wall of the capacitor. Therefore, such product 106 causes a short circuit between the upper electrode 103 and the lower electrode 101.
The fact that the reaction product is adhered to the side wall of the capacitor, that is patterned by using the resist as a mask, is also set forth in Patent Application Publication (KOKAI) Hei 10-98162.
In order to prevent the adhesion of the etching product onto the side wall of the capacitor, as shown in FIG. 3A or FIG. 3B, it is normal to form the second resist pattern 104 or the third resist pattern 105 wider than the width of the upper electrode 103 such that the etching product can be prevented from adhering onto the side wall of the overall capacitor.
The extended width of the second resist pattern 104 or the third resist pattern 105 from the upper electrode 103 must be set the length that is obtained by adding the margin to the displacement control range in the photolithography step.
Accordingly, the sectional shape of the capacitor is given as shown in FIG. 3C after the formation of the capacitor is completed. Thus, the side surface of the upper electrode 103 and the side surface of the lower electrode 101 are not positioned on the same plane and thus formed in tiers to have a level difference. A planar shape of the capacitor is shown in FIG. 4.
However, according to the capacitor forming method shown in FIGS. 3A to 3D, the short between the upper electrode and the lower electrode via the etching product can be prevented. In this case, the miniaturization of the capacitor is disturbed since, as shown in FIG. 4, the width of the lower electrode 101 must be formed larger than the upper electrode 103 by for example about 0.45 μm on one side because of the displacement of the exposure equipment and the marginal width.